
; not so long shift register for 64k DRAMs
; (c) 2001 René Schmitz
; uzs159@uni-bonn.de
; http://www.uni-bonn.de/~uzs159


.include "c:\programme\Atmel\AVR Studio\1200def.inc"
.cseg

.org 0

	.def NUL = R16
	.def ADR0 = R23
	.def ONE = R20
	.def ADR1 = R22
	
RESET:
	ser R17            
	ldi ONE, $1
	out DDRB, R17
	out DDRD,R17
	ldi NUL,0
	out portd,r17
	out portb,r17
	ldi ADR0,0
	ldi ADR1,0

; this is much slower than the 256k version due to the use of CBI which consumes 2 cycles.
; I wonder, because thats the same as doing ORI or ANDI and then send OUT ?!
; I think that could also be done by a macro !!
	
STRTT:
	out PORTD, r17     ; Start out with all bits set
	out PORTB, ADR0    ; send out lower half of address
	cbi PORTD, 0	   ; clearing RAS strobes the address
	out PORTB, ADR1    ; send upper half of address
	cbi PORTD, 1       ; clearing CAS strobes the address
	cbi PORTD, 2       ; clearing R/'W makes it write
	add ADR0, one      ; increment the address counter
	adc ADR1, NUL      ; 
		
	rjmp STRTT         ; back to start
	
	
